The present invention relates to a buffer circuit, more particularly, to a buffer circuit including a flip-flop which receives an external input and produces complementary outputs thereof.
The above-mentioned buffer circuit is currently used, for example, in the input stage of data input circuits and the input stage of memory circuits, as an address buffer. The present invention, applicable to various other buffer circuits as well, will be explained in reference to address buffers.
Address buffers are incorporated into dynamic memories at their input stages to supply complementary addresses to decoders for accessing a desired memory cell in the memory. Such address buffers are mainly comprised of flip-flops provided with a pair of input/output terminals. The flip-flops receive an external address at one of the input terminals and produce complementary external addresses at the output terminals.
Buffer circuits currently used suffer from a defect in that the flip-flop cannot be changed to a stable state quickly. It is necessary to wait a certain amount of time until the flip-flop is completely in its stable state with the result that complementary external addresses cannot be produced in a short time. The reason for this will be clarified hereinafter. If such a buffer circuit is used as an address buffer in a dynamic memory, it would prevent the memory from operating at a high speed.